A phase locked loop or phase-locked loop (PLL) is a control system that generates an output signal, also called a F_N clock, whose phase is related to the phase of an input “reference” signal, also called a F_ref clock.
After a PLL is powered on, the F_ref clock has initial phase error with the F_N clock, which ranges from 0 to 2π. The PLL can only start a locking operation after the phase error has been cancelled.